Lead Functional Formal Verification Engineer

Role Overview We are seeking a senior and experienced Functional Formal Verification Engineer to join our team in Bengaluru and lead formal verification efforts for complex digital designs. In this role, you will play a critical part in ensuring the quality and reliability of our digital designs and IP blocks. You will collaborate with cross-functional design teams and mentor junior engineers in formal verification methodologies. Key Responsibilities - Lead complete formal verification for design blocks and IPs, including developing verification strategies and test plans. - Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. - Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures. - Develop reusable and optimized formal models and verification code bases. - Mentor junior team members and train them on industry-standard tools and techniques. Required Qualifications - Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. - 5 or more years of experience in formal verification of complex IP, SubSystem, or SoCs. - Expertise in formal verification tools, property specification languages like SVA or PSL, and HDLs like System Verilog. - Experience with scripting languages such as Python, Tcl, or Perl, and programming in C/C++ or SystemC. - Strong analytical and debugging skills with experience working in team environments. Why Join Us Join MediaTek to work on cutting-edge semiconductor designs that power the world's most advanced devices. We offer a highly collaborative environment with ample opportunities for technical leadership and growth.

- Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering. - 5+ years of experience in formal verification of complex IP/SubSystem/SoCs. - Strong understanding of digital logic design and verification techniques. - Expertise in formal verification tools and property specification languages (SVA, PSL). - Proficiency in HDLs such as System Verilog, Verilog, or VHDL. - Experience with scripting (Python, Tcl, Perl) and programming (C/C++, SystemC). - Excellent debugging, problem-solving, and analytical skills. - Proven track record of technical leadership and mentoring.

- Competitive compensation package. - Comprehensive health and wellness benefits. - Opportunities for career growth and professional development. - Collaborative work environment with top industry experts. - Paid time off and holiday benefits.