HIring for ASIC verification
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Job Description
JD for ASIC verification engineers: 5-8 years: 2 positions
- -Implement verification environment independently using high level verification languages like System Verilog
- OVM/UVM methodology based implementation
- Experience on Synopsys VCS/ Mentor Questa
- -Understand and execute the existing verification flows and improve the framework
- -Contribute to verification methodology development and implementation
Job Requirements
- -Knowledge of FPGA design and development flow is a plus
BE/B Tech/ME/M Tech - Electronics
Key Requirements & Skills
- -Knowledge of FPGA design and development flow is a plus
BE/B Tech/ME/M Tech - Electronics
Frequently Asked Questions
How to apply for HIring for ASIC verification at Happiest Minds?
Click the "Apply via CareerScan" button on this page.
What is the salary for this role?
Salary details will be discussed during the interview.
What experience is required?
Senior of experience is required.
Is this position still open?
Yes, currently active and accepting applications.
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HIring for ASIC verification
Happiest Minds · Bengaluru