Timing closure expert

Change the world. Love your job.

In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.

As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.

This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.

• Minimum requirements:

• 5+ years of relevant experience

• A thorough understanding of timing closure aspects

• Ability to solve problems using a systematic approach

• Preferred qualifications:

• Define and drive SOC timing closure strategy across the flow ( synthesis, placement, CTS and signoff)

• Collaborate with architecture, RTL, DFT  and verification teams to ensure design intent is preserved.

• Drive

ECO (Engineering Change Order)

 implementation for functional and timing fixes.

• Analyze and resolve

PPA trade-offs

 using advanced EDA tools and methodologies.

• Knowledge of

DFT (Design for Test)

 and 

basic layout aspects

• Interest in adopting AI/ML techniques along with flow automations

• Define and drive SOC timing closure strategy across the flow ( synthesis, placement, CTS and signoff)
• Collaborate with architecture, RTL, DFT  and verification teams to ensure design intent is preserved.
• Drive

ECO (Engineering Change Order)

 implementation for functional and timing fixes.

• Analyze and resolve

PPA trade-offs

 using advanced EDA tools and methodologies.

• Knowledge of

DFT (Design for Test)

 and 

basic layout aspects

• Interest in adopting AI/ML techniques along with flow automations