Staff Engineer Design

#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?

Your Role

Key responsibilities in your new role

• Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools
• Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility,timing and power
• Write and implement block level and top-level constraints for synthesis, perform timing closure and power analysis
• Develop and implement synthesis flows and methodologies, and driveimprovements in the design process
• Debug and resolve design issues related to synthesis, timing, power, and area
• Understanding of DFT flows, including scan insertion and ATPG
• Optimize designs for power,performance, are and meet design goals within the given schedule
• Implement pipelining at different levels for performance optimization and timing closure
• Perform power analysis and optimize designs for low power

Your Profile

Qualifications and skills to help you succeed

• B.Tech/M.Tech in Electronics or related field with 8+ years of relevant experience
• Strong fundamentals in Synthesis and STA, with hands-on experience in timing sign-off, margin calculations, and leading STA for full-chip projects
• Expertise in MCMM analysis, multi-power domain designs, constraint mode merging, and STA flow development with bottleneck identification
• Proficient in SDC constraints, timing ECO generation, and driving TAT reduction across complex designs
• Experience collaborating closely with Design and Physical Design teams to meet aggressive schedules
• Skilled in Synopsys/Cadence EDA tools, with scripting knowledge in Tcl/Perl as an added advantage
• Strong analytical, communication, and mentoring skills with ability to work across cross-functional and global teams.
• Proficient with EDA tools from Synopsys/Cadence/Mentor

• Contact:
  Gowri Shenoy, LinkedIn

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?

We are on a journey to create the best Infineon for everyone.

This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
Click here for more information about Diversity & Inclusion at Infineon.

• B.Tech/M.Tech in Electronics or related field with 8+ years of relevant experience
• Strong fundamentals in Synthesis and STA, with hands-on experience in timing sign-off, margin calculations, and leading STA for full-chip projects
• Expertise in MCMM analysis, multi-power domain designs, constraint mode merging, and STA flow development with bottleneck identification
• Proficient in SDC constraints, timing ECO generation, and driving TAT reduction across complex designs
• Experience collaborating closely with Design and Physical Design teams to meet aggressive schedules
• Skilled in Synopsys/Cadence EDA tools, with scripting knowledge in Tcl/Perl as an added advantage
• Strong analytical, communication, and mentoring skills with ability to work across cross-functional and global teams.
• Proficient with EDA tools from Synopsys/Cadence/Mentor