𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀
𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟯𝟲𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟬-𝟯𝟲 𝗟𝗣𝗔)
Experience: 7+ yrs
Location: Bengaluru, Karnataka
Job Type: Full-time
We are looking for a highly experienced
RTL Integration Engineer
to lead complex
SoC and subsystem RTL integration
for next-generation semiconductor products. The role requires strong expertise in SystemVerilog/Verilog, digital design, AMBA protocols, static verification, timing constraints, and integration automation.
You will be responsible for integrating multi-million-gate SoCs and complex third-party IPs, ensuring design quality and integration readiness across the development lifecycle. The role involves close collaboration with
Architecture, Design Verification, DFT, Synthesis, Physical Design, and other cross-functional teams
to resolve integration issues and drive designs toward successful tapeout.
Requirements
KEY RESPONSIBILITIES
RTL integration
of multi-million-gate SoCs, subsystems, and complex third-party IPs.
PCIe, DDR, Ethernet, ARM/RISC-V cores
, and other internal or external design blocks using SystemVerilog and Verilog.
- Configure and assemble SoC interconnect fabrics using
AMBA AXI4, AHB, APB, and CHI
protocols.
- Define and validate IP integration specifications, connectivity, configuration, clocking, resets, and interface requirements.
- Own and execute static RTL quality and sign-off flows, including
Lint, CDC, RDC, and low-power intent checks
.
SpyGlass, Questa CDC, VC SpyGlass
, or equivalent static verification platforms.
- Develop, maintain, and validate
SDC timing constraints
for top-level and subsystem designs.
- Collaborate closely with Synthesis and Physical Design teams to resolve timing, area, congestion, and power-related issues.
- Analyse integration and implementation results and drive corrective actions across relevant design teams.
- Drive
functional and timing ECOs
during late stages of the development cycle.
- Develop and maintain automated RTL build, compilation, integration, and validation flows.
- Use
Python, TCL, Perl, and Shell scripting
to automate repetitive integration and verification activities.
- Debug complex full-chip RTL, connectivity, clocking, reset, timing, and integration issues.
- Collaborate with
Architecture, Design Verification, DFT, Synthesis, and Physical Design teams
to ensure high-quality design handoffs.
- Support design reviews, integration sign-off, release activities, and tapeout readiness.
- Identify opportunities to improve RTL integration methodology, automation, quality checks, and engineering workflows.
- Mentor junior engineers and provide technical guidance on RTL integration, static checks, debugging, and design best practices.
- Maintain integration documentation, specifications, scripts, and technical sign-off requirements.
WHAT MAKES YOU A GREAT FIT
7+ years of hands-on experience
in SoC or subsystem RTL integration within the
VLSI/Semiconductor industry
.
SystemVerilog and Verilog
with a solid understanding of digital design principles.
- Proven experience integrating complex SoCs, subsystems, and third-party IPs in multi-million-gate designs.
- In-depth understanding of
AMBA protocols
, particularly AXI4, AHB, APB, and CHI.
- Strong understanding of SoC interconnect, memory-controller interfaces, IP integration, and subsystem architecture.
- Hands-on experience with
Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and UPF/CPF low-power intent checks
.
- Experience with static verification and sign-off tools such as
SpyGlass, Questa CDC, VC SpyGlass
, or equivalent.
logical synthesis, SDC timing constraints, timing analysis, and Physical Design interfaces
.
- Experience identifying and resolving timing, area, power, and integration issues in collaboration with Synthesis and Physical Design teams.
- Proven experience executing
functional and timing ECOs
during late-stage design cycles.
- Strong scripting and automation skills using
Python, TCL, Perl, and/or Shell
.
- Experience developing automated RTL build, integration, validation, and regression workflows.
- Strong debugging and diagnostic skills with the ability to resolve complex full-chip integration issues.
- Understanding of SoC design flows, verification methodologies, DFT interfaces, low-power design, and tapeout processes.
- Strong cross-functional communication and collaboration skills.
- Ability to mentor junior engineers and provide technical leadership within an integration team.
- Strong ownership mindset with a demonstrated ability to drive complex semiconductor designs toward
sign-off and tapeout
.
- B.E./B.Tech/M.E./M.Tech in
Electrical Engineering, Electronics Engineering, VLSI, or a related discipline
is preferred.
