Senior Physical Design Engineer - Server SoC & Chiplet Implementation

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• THE ROLE:

The focus of this role is to plan, build, and execute the Physical Design for complex Chiplets in Server SoC in advanced technology nodes.

• KEY RESPONSIBILITIES:

• Hands on experience with Block level and Top-level physical implementation.
• Good understanding and hands-on experience in lower node technologies. (5nm or below)
• Drive the design and implementation of large design blocks from initial concept through to tape-out.
• Execute synthesis for high-speed designs and lead the Place and Route processes while meticulously analyzing design results for optimization.
• Collaborate closely with cross-functional teams, including RTL/Logic designers, to facilitate seamless integration and problem resolution.
• Demonstrate strong problem-solving and work well with cross-functional teams
• Good listening, writing, and speaking English
• Good communication skills, strong interpersonal skills and flexibility
• Dedicated, hardworking and good team player
• Familiar with Unix/Linux environment and good at scripts

• PREFERRED EXPERIENCE:

• Hands on experience in place and route flows including multi-voltage designs
• Hands on experience in industry standard Place & Route tools such as Fusion Compiler , ICC2 and Innovus
• Hands on experience with any of synthesis, STA, or physical verification domains
• Strong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage areas, power-state tables, electrical checks using FM & VSI
• Good control over scripting languages like Python, PERL, TCL and strong debug capabilities

• ACADEMIC CREDENTIALS:

• Masters or Bachelor’s degree in Electronics Engineering
• 8-12 years of experience in Physical Design flow and methodology development on advanced nodes such as 5nm & 3nm
• Proficiency in or more scripting languages namely Tcl, Perl, sed/awk
• Strong problem-solving skills and analytical thinking
• Team player, good work ethic, and excellent communication skills

#LI-PK2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

• 8-12 years of experience in Physical Design flow and methodology development on advanced nodes such as 5nm & 3nm
• Hands on experience with Block level and Top-level physical implementation
• Experience in lower node technologies (5nm or below)
• Proficiency in scripting languages like Tcl, Perl, sed/awk
• Masters or Bachelor’s degree in Electronics Engineering
• Hands on experience in place and route flows including multi-voltage designs
• Experience with industry standard Place & Route tools such as Fusion Compiler, ICC2 and Innovus
• Experience with synthesis, STA, or physical verification domains
• Understanding of low-power flows including UPF concepts, power-gating, isolation, level-shifter, voltage areas, power-state tables, electrical checks using FM & VSI
• Control over scripting languages like Python