Senior DFT Design Engineer, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Senior DFT Design Engineer, you will define, design, analyze the DFT implementation and flow, that supports the systems that are the heart of the world's largest and most powerful computing infrastructure. The team develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high volume manufacturing. You will shape the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high speed iOS, Analog DFT).
• Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
• Insert DFT logic, boundary scan, scan chains, DFT compression, logic BIST, TAP controller, clock control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• Experience in fault modeling.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for multi die SoCs).
• Experience in SoC cycles, silicon bringup, and silicon debug activities.

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• Experience in fault modeling.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for multi die SoCs).
• Experience in SoC cycles, silicon bringup, and silicon debug activities.