Principal Verification Engineer, Design

**Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities include, but not limited to:

- Full-chip functional verification on Micron’s non-volatile memory design projects

• You thoroughly understand design specs and develop verification plans for various designs.

• Test bench Development in System Verilog targeting complete functionality coverage.

• Support of System Verilog assertion and coverage-driven methodology

• Support of design verification methodology improvements

• Run directed and constrained-random verification tests.

• You will think through design corner cases and be able to write relevant cover points.

• Collaborate with digital design team to debug test cases and deliver functionally accurate designs.

• Close coverage measures to identify verification holes and to show progress towards tape-out.

• Development of Micron’s NAND Flash behavioral models in System Verilog.

• Technical support to internal and external model users

• Complete verification on Micron’s NAND Flash models based on design datasheet.

• Collaboration with Application engineers on design datasheet and model requirements

• Driving innovation into the future Memory generations within a multifaceted work environment

• Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies

• Leverage AI tools to automate the tools and workflow

  Applying Artificial Intelligence in workflows to improve build efficiency

Minimum Qualifications:

- MS or BS degree in Electrical or Computer Engineering or equivalent

• 7-15 of experience developing verification collateral in Verilog, System Verilog and UVM
• UVM Proficiency is a must.
• Prior work experience with complex coverage driven random constraint UVM environments.
• Putting together complex UVM environments from scratch is a requirement.
• Deep knowledge on circuit design, digital logic, and logic verification methodology
• Understanding on Verilog RTL coding, System Verilog object-oriented language
• Good knowledge on programming language such as C++, and scripting language like TCL and PERL

About Micron Technology, Inc.**

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_[email protected]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

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• : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification
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• MS or BS degree in Electrical or Computer Engineering or equivalent
• 7-15 of experience developing verification collateral in Verilog, System Verilog and UVM
• UVM Proficiency is a must.
• Prior work experience with complex coverage driven random constraint UVM environments.
• Putting together complex UVM environments from scratch is a requirement.
• Deep knowledge on circuit design, digital logic, and logic verification methodology
• Understanding on Verilog RTL coding, System Verilog object-oriented language
• Good knowledge on programming language such as C++, and scripting language like TCL and PERL