Principal STA Engineer

About Analog Devices

Analog Devices, Inc. (NASDAQ: https://finance.yahoo.com/quote/ADI/?ltr=1 ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at https://www.analog.com/en.html www.analog.com and on https://www.linkedin.com/company/analog-devices LinkedIn and https://x.com/ADI_News X.

• Job Description: We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include

• STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis, and timing closure at Partition/Sub-system/FC level.
• Driving Convergence by  influencing APR, Design teams  stakeholders
• Familiar with Constraint development and clean up.
• Good understanding of different CTS strategies and providing the feedback to Implementation Team.
• Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows.
• Work on Automation scripts with in STA tools for Methodology development.
• Excellent debugging skills in implementation issues and ability to come up with creative solutions.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Familiar with digital design Implementation RTL to GDSII : Synopsys/Cadence tools.
• Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics especially 28nm and below technology nodes.
• Handson experience on timing closure  industry standard  high speed interfaces like DDR, PCIE, HBM, D2D

• Qualification:

• 12+  Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
• Must have led at least 2 SOCs in capacity of SOC Sign-off lead especially. Solid Expertise in Primetime or Similar timing tools
• good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
• Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
• Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced          

Required Travel: Yes, 10% of the time          

Shift Type: 1st Shift/Days

• 12+  Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.
• Must have led at least 2 SOCs in capacity of SOC Sign-off lead especially. Solid Expertise in Primetime or Similar timing tools
• good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
• Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
• Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important