Scan your resume against ATS criteria for this Lead Design Engineer role at Cadence.
3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.
How to apply for Lead Design Engineer at Cadence?
Click the "Apply on Company Website" button on this page to submit your application directly on the employer's official portal.
What is the salary for this role?
Salary details will be discussed during the interview.
What experience is required?
This position is open to freshers and experienced candidates.
Is this position still open?
Yes, currently active and accepting applications.
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