Overview:
We are seeking a highly skilled
ASIC Verification Engineer (IP & SoC)
with 5 to 10 years of hands-on experience in semiconductor verification. The ideal candidate will be responsible for defining and executing verification strategies for complex IPs and SoCs, developing scalable UVM-based verification environments, and validating high-speed protocols such as AMBA AXI and PCIe. This role requires strong debugging expertise, automation skills, and experience working with industry-standard EDA verification tools
Verification Planning & Execution
- Define, develop, and execute comprehensive verification plans at both IP and SoC levels.
- Drive verification closure through functional coverage, code coverage, assertions, and regression analysis.
- Develop verification methodologies aligned with project requirements and quality standards.
Testbench Architecture & Development
- Architect and develop scalable, reusable constrained-random verification environments using
SystemVerilog and UVM
.
- Create verification components, scoreboards, monitors, checkers, and reusable testbench infrastructure.
- Develop and execute directed, random, and stress test scenarios.
AMBA AXI Verification
AXI3, AXI4, and AXI5
based subsystems.
- Validate AXI Interconnects, NoCs (Network-on-Chip), and multi-layer bus architectures.
- Analyze and verify out-of-order transaction handling, latency optimization, and bandwidth performance.
PCIe Sub-System Verification
- Verify PCIe Gen3, Gen4, Gen5, and Gen6 controller functionality across Physical, Data Link, and Transaction Layers.
- Validate high-performance DMA engines operating in Endpoint and Root Complex configurations.
- Ensure protocol compliance and robust performance under various traffic conditions.
Protocol & Performance Verification
- Verify high-speed industry-standard protocols and ensure compliance with protocol specifications.
- Execute performance verification to validate throughput, latency, and system-level behavior.
- Support low-power verification methodologies using UPF/CPF where applicable.
Debugging & Failure Analysis
- Debug complex simulation failures and identify root causes in RTL designs.
- Perform protocol-level debugging and waveform analysis.
- Collaborate closely with design, architecture, and software teams to resolve issues efficiently.
Gate-Level Simulation (GLS)
- Set up and execute gate-level simulations with and without timing annotations.
- Analyze timing-related issues and support pre-silicon signoff activities.
Automation & Productivity Enhancement
- Develop automation scripts using Python, Perl, or Tcl.
- Improve regression execution, result analysis, coverage tracking, and verification workflows
Education
- Bachelor's or Master's degree in Electronics, Communication Engineering, VLSI, Computer Engineering, or a related field.
Experience
- 5 to 10 years of proven experience in ASIC/SoC verification.
- Strong background in IP-level and SoC-level verification projects.
Technical Skills
SystemVerilog and UVM
.
- Hands-on experience with constrained-random verification methodologies.
- Solid understanding of AMBA AXI protocols (AXI3/4/5).
- Experience in verifying PCIe Gen3/4/5/6 subsystems.
- Knowledge of Network-on-Chip (NoC), interconnect architectures, and DMA engines.
- Experience with protocol compliance, functional coverage, assertions, and verification closure.
Low Power & Performance Verification
- Experience with low-power verification using
UPF/CPF
(preferred).
- Understanding of performance verification techniques and system-level analysis.
Automation Skills
- Proficiency in scripting using
Python, Perl, or Tcl
.
- Experience automating verification and regression environments.
EDA Tools
Hands-on experience with or more industry-standard simulators:
- Synopsys VCS
- Cadence Xcelium
- Siemens Questa/QuestaSim
Preferred Qualifications
- Experience with gate-level simulations and timing analysis.
- Exposure to advanced verification methodologies and reusable verification IPs.
- Strong debugging, communication, and problem-solving skills.
- Ability to work effectively in a fast-paced product development environment.
